Sciweavers

1093 search results - page 119 / 219
» Verifying VLSI Circuits
Sort
View
129
Voted
ISSS
2002
IEEE
141views Hardware» more  ISSS 2002»
15 years 7 months ago
An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems
Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and r...
Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin
IJCNN
2000
IEEE
15 years 7 months ago
Analog Hardware Implementation of the Random Neural Network Model
This paper presents a simple continuous analog hardware realization of the Random Neural Network (RNN) model. The proposed circuit uses the general principles resulting from the u...
Hossam Abdelbaki, Erol Gelenbe, Said E. El-Khamy
164
Voted
CODES
2008
IEEE
15 years 4 months ago
Design and defect tolerance beyond CMOS
It is well recognized that novel computational models, devices and technologies are needed in order to sustain the remarkable advancement of CMOS-based VLSI circuits and systems. ...
Xiaobo Sharon Hu, Alexander Khitun, Konstantin K. ...
ECCC
2000
158views more  ECCC 2000»
15 years 2 months ago
On the Computational Power of Winner-Take-All
This article initiates a rigorous theoretical analysis of the computational power of circuits that employ modules for computing winner-take-all. Computational models that involve ...
Wolfgang Maass
ISVLSI
2008
IEEE
104views VLSI» more  ISVLSI 2008»
15 years 9 months ago
Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations
In high-performance VLSI circuits, the on-chip power densities are playing dominant role due to increased scaling of technology, increasing number of components, frequency and ban...
Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Pa...