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» Verifying VLSI Circuits
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ISSS
2002
IEEE
141views Hardware» more  ISSS 2002»
14 years 1 months ago
An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems
Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and r...
Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin
IJCNN
2000
IEEE
14 years 1 months ago
Analog Hardware Implementation of the Random Neural Network Model
This paper presents a simple continuous analog hardware realization of the Random Neural Network (RNN) model. The proposed circuit uses the general principles resulting from the u...
Hossam Abdelbaki, Erol Gelenbe, Said E. El-Khamy
CODES
2008
IEEE
13 years 10 months ago
Design and defect tolerance beyond CMOS
It is well recognized that novel computational models, devices and technologies are needed in order to sustain the remarkable advancement of CMOS-based VLSI circuits and systems. ...
Xiaobo Sharon Hu, Alexander Khitun, Konstantin K. ...
ECCC
2000
158views more  ECCC 2000»
13 years 8 months ago
On the Computational Power of Winner-Take-All
This article initiates a rigorous theoretical analysis of the computational power of circuits that employ modules for computing winner-take-all. Computational models that involve ...
Wolfgang Maass
ISVLSI
2008
IEEE
104views VLSI» more  ISVLSI 2008»
14 years 3 months ago
Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations
In high-performance VLSI circuits, the on-chip power densities are playing dominant role due to increased scaling of technology, increasing number of components, frequency and ban...
Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Pa...