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» Verifying VLSI Circuits
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GLVLSI
2003
IEEE
132views VLSI» more  GLVLSI 2003»
14 years 2 months ago
Power-aware pipelined multiplier design based on 2-dimensional pipeline gating
Power-awareness indicates the scalability of the system energy with changing conditions and quality requirements. Multipliers are essential elements used in DSP applications and c...
Jia Di, Jiann S. Yuan
GLVLSI
2003
IEEE
140views VLSI» more  GLVLSI 2003»
14 years 2 months ago
Exploiting multiple functionality for nano-scale reconfigurable systems
It is likely that it will become increasingly difficult to manufacture the complex, heterogeneous logic structures that characterise current reconfigurable logic systems. As a res...
Paul Beckett
GLVLSI
2002
IEEE
106views VLSI» more  GLVLSI 2002»
14 years 1 months ago
A low power direct digital frequency synthesizer with 60 dBc spectral purity
We present a low-power sine-output Direct Digital Frequency Synthesizer (DDFS) realized in 0.18 µm CMOS that achieves 60 dBc spectral purity from DC to the Nyquist frequency. No ...
J. M. Pierre Langlois, Dhamin Al-Khalili
VLSID
1999
IEEE
88views VLSI» more  VLSID 1999»
14 years 1 months ago
New and Exact Filling Algorithms for Layout Density Control
To reduce manufacturing variation due to chemicalmechanical polishing and to improve yield, layout must be made uniform with respect to density criteria. This is achieved by layou...
Andrew B. Kahng, Gabriel Robins, Anish Singh, Alex...
GLVLSI
2007
IEEE
328views VLSI» more  GLVLSI 2007»
14 years 3 months ago
New timing and routability driven placement algorithms for FPGA synthesis
We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...
Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong H...