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» Verifying VLSI Circuits
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TCAD
2002
128views more  TCAD 2002»
13 years 8 months ago
Preferred direction Steiner trees
Interconnect optimization for VLSI circuits has received wide attention. To model routing surfaces, multiple circuit layers are freabstracted as a single rectilinear plane, ignori...
Mehmet Can Yildiz, Patrick H. Madden
GLVLSI
2003
IEEE
180views VLSI» more  GLVLSI 2003»
14 years 2 months ago
3D direct vertical interconnect microprocessors test vehicle
The current trends in high performance integrated circuits are towards faster and more powerful circuits in the giga-hertz range and even further. As the more complex Integrated C...
John Mayega, Okan Erdogan, Paul M. Belemjian, Kuan...
VLSID
2009
IEEE
87views VLSI» more  VLSID 2009»
14 years 9 months ago
Soft Error Rates with Inertial and Logical Masking
We analyze the neutron induced soft error rate (SER). An induced error pulse is modeled by two parameters, probability of occurrence and probability density function of the pulse ...
Fan Wang, Vishwani D. Agrawal
VLSID
2009
IEEE
150views VLSI» more  VLSID 2009»
14 years 9 months ago
TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis
We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully ...
Alejandro Czutro, Ilia Polian, Matthew D. T. Lewis...
VLSID
2008
IEEE
83views VLSI» more  VLSID 2008»
14 years 9 months ago
Efficient Linear Macromodeling via Discrete-Time Time-Domain Vector Fitting
We present a discrete-time time-domain vector fitting algorithm, called TD-VFz, for rational function macromodeling of port-to-port responses with discrete time-sampled data. The ...
Chi-Un Lei, Ngai Wong