1093 search results - page 141 / 219 » Verifying VLSI Circuits |
GLVLSI
2009
IEEE
14 years 3 months ago
2009
IEEE
Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutio...
GLVLSI
2009
IEEE
14 years 3 months ago
2009
IEEE
Recently, cooperative communication has attracted a lot of attention for its potential to increase spatial diversity. However, limited attention has been paid to the physical laye...
GLVLSI
2009
IEEE
14 years 3 months ago
2009
IEEE
In the context of formal verification Bounded Model Checking (BMC) has shown to be very powerful for large industrial designs. BMC is used to check whether a circuit satisfies a...
GLVLSI
2009
IEEE
14 years 3 months ago
2009
IEEE
Networks-on-Chip (NoCs) become a critical design factor as chip multiprocessors (CMPs) and systems on a chip (SoCs) scale up with technology. With fundamental benefits of high ban...
GLVLSI
2008
IEEE
14 years 3 months ago
2008
IEEE
Novel nano-scale devices have shown promising potential to overcome physical barriers faced by complementary metaloxide semiconductor (CMOS) technology in future circuit design. H...