An embedded 40 MHz FIFO buffer for use in mixed-signal information processing applications is presented. The buffer design uses a 1T DRAM topology for its unit memory cell compone...
Michael I. Fuller, James P. Mabry, John A. Hossack...
Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on adjacent wires on long bus lines can increase delay...
Abstract—Antenna problem is a phenomenon of plasma-induced gateoxide degradation. It directly affects manufacturability of very large scale integration (VLSI) circuits, especiall...
Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong,...
We propose an algorithm for gate-delay fault diagnosis. It is based on the inject-and-evaluate paradigm [1], in which the fault site(s) are predicted through a series of injection...
This paper presents three reconfigurable computing approaches for a Shape-Adaptive Template Matching (SA-TM) method to retrieve arbitrarily shaped objects within images or video f...