1093 search results - page 145 / 219 » Verifying VLSI Circuits |
GLVLSI
2003
IEEE
14 years 2 months ago
2003
IEEE
An embedded 40 MHz FIFO buffer for use in mixed-signal information processing applications is presented. The buffer design uses a 1T DRAM topology for its unit memory cell compone...
SLIP
2003
ACM
14 years 2 months ago
2003
ACM
Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on adjacent wires on long bus lines can increase delay...
DATE
2002
IEEE
14 years 1 months ago
2002
IEEE
Abstract—Antenna problem is a phenomenon of plasma-induced gateoxide degradation. It directly affects manufacturability of very large scale integration (VLSI) circuits, especiall...
DFT
2002
IEEE
14 years 1 months ago
2002
IEEE
We propose an algorithm for gate-delay fault diagnosis. It is based on the inject-and-evaluate paradigm [1], in which the fault site(s) are predicted through a series of injection...
FCCM
2002
IEEE
14 years 1 months ago
2002
IEEE
This paper presents three reconfigurable computing approaches for a Shape-Adaptive Template Matching (SA-TM) method to retrieve arbitrarily shaped objects within images or video f...