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» Verifying VLSI Circuits
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FCCM
2007
IEEE
165views VLSI» more  FCCM 2007»
13 years 10 months ago
Sparse Matrix-Vector Multiplication Design on FPGAs
Creating a high throughput sparse matrix vector multiplication (SpMxV) implementation depends on a balanced system design. In this paper, we introduce the innovative SpMxV Solver ...
Junqing Sun, Gregory D. Peterson, Olaf O. Storaasl...
ISLPED
2010
ACM
206views Hardware» more  ISLPED 2010»
13 years 9 months ago
Energy efficient implementation of parallel CMOS multipliers with improved compressors
Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under...
Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija
GLVLSI
2010
IEEE
168views VLSI» more  GLVLSI 2010»
13 years 9 months ago
A revisit to voltage partitioning problem
We revisit voltage partitioning problem when the mapped voltages of functional units are predetermined. If energy consumption is estimated by formulation E = CV 2 , a published wo...
Tao Lin, Sheqin Dong, Bei Yu, Song Chen, Satoshi G...
GLVLSI
2008
IEEE
150views VLSI» more  GLVLSI 2008»
13 years 9 months ago
Using unsatisfiable cores to debug multiple design errors
Due to the increasing complexity of today's circuits a high degree of automation in the design process is mandatory. The detection of faults and design errors is supported qu...
André Sülflow, Görschwin Fey, Rod...
HEURISTICS
2002
99views more  HEURISTICS 2002»
13 years 8 months ago
Parallelizing Tabu Search on a Cluster of Heterogeneous Workstations
In this paper, we present the parallelization of tabu search on a network of workstations using PVM. Two parallelization strategies are integrated: functional decomposition strate...
Ahmad A. Al-Yamani, Sadiq M. Sait, Habib Youssef, ...