NBTI (Negative Bias Temperature Instability) has emerged as the dominant PMOS device failure mechanism for sub100nm VLSI designs. There is little research to quantify its impact o...
In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto front is introduced as a useful analysis tool to explore the design space of e...
Roberto Pereira-Arroyo, Pablo Alvarado-Moya, Wolfg...
— A VLSI hardware architecture for the on-chip implementation of a first-order 3D IIR fully-multiplexed frequencyplanar filter module (FMFPM) is proposed. FMFPMs may be employed ...
— We propose a VLSI architecture for the single-chip realization of 2D spatio-temporal IIR digital filters, consisting of a meshed connection of concurrent identical vector-proce...
Abstract—Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polariti...