Sciweavers

1093 search results - page 157 / 219
» Verifying VLSI Circuits
Sort
View
IPPS
2006
IEEE
14 years 2 months ago
Parallelizing post-placement timing optimization
This paper presents an efficient modeling scheme and a partitioning heuristic for parallelizing VLSI post-placement timing optimization. Encoding the paths with timing violations...
Jiyoun Kim, Marios C. Papaefthymiou, José N...
ISVLSI
2006
IEEE
115views VLSI» more  ISVLSI 2006»
14 years 2 months ago
The Design of Analog Front-End Circuitry for 1X HD-DVD PRML Read Channel
In this paper, the design techniques and considerations for each building block required for analog signal processing in HD-DVD PRML read channel are presented and the procedures ...
Sheng-Jang Lin, I-Shun Chen, Bo-Wei Chen, Feng-Hsi...
DATE
2005
IEEE
107views Hardware» more  DATE 2005»
14 years 2 months ago
On Statistical Timing Analysis with Inter- and Intra-Die Variations
In this paper, we highlight a fast, effective and practical statistical approach that deals with inter and intra-die variations in VLSI chips. Our methodology is applied to a numb...
Hratch Mangassarian, Mohab Anis
SBCCI
2005
ACM
112views VLSI» more  SBCCI 2005»
14 years 2 months ago
New low-voltage electrically tunable triode-MOSFET transconductor and its application to low-frequency Gm-C filtering
A new low-voltage electrically tunable transconductor is presented. Its transconductance can be settled by means of a ratio between a reference current and a reference voltage ren...
Carlos Dualibe, Pablo A. Petrashin, Luis E. Toledo...
ISPD
2004
ACM
120views Hardware» more  ISPD 2004»
14 years 2 months ago
Multilevel routing with antenna avoidance
As technology advances into nanometer territory, the antenna problem has caused significant impact on routing tools. The antenna effect is a phenomenon of plasmainduced gate oxide...
Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen