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» Verifying VLSI Circuits
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VTS
2002
IEEE
138views Hardware» more  VTS 2002»
14 years 1 months ago
Test Power Reduction through Minimization of Scan Chain Transitions
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test v...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
VTS
2002
IEEE
128views Hardware» more  VTS 2002»
14 years 1 months ago
Power Supply Transient Signal Analysis Under Real Process and Test Hardware Models
A device testing method called Transient Signal Analysis (TSA) is subjected to elements of a real process and testing environment in this paper. Simulations experiments are design...
Abhishek Singh, Jim Plusquellic, Anne E. Gattiker
ASPDAC
2000
ACM
80views Hardware» more  ASPDAC 2000»
14 years 1 months ago
An interleaved dual-battery power supply for battery-operated electronics
 After a detailed analysis and discussion of two important characteristics of today’s battery cells (i.e., their current-capacity and current-voltage curves), this paper descr...
Qing Wu, Qinru Qiu, Massoud Pedram
DAC
2000
ACM
14 years 1 months ago
Modeling and simulation of real defects using fuzzy logic
Real defects (e.g. stuck-at or bridging faults) in the VLSI circuits cause intermediate voltages and can not be modeled as ideal shorts. In this paper we first show that the trad...
Amir Attarha, Mehrdad Nourani, Caro Lucas
DATE
1998
IEEE
141views Hardware» more  DATE 1998»
14 years 1 months ago
Address Bus Encoding Techniques for System-Level Power Optimization
The power dissipated by system-level buses is the largest contribution to the global power of complex VLSI circuits. Therefore, the minimization of the switching activity at the I...
Luca Benini, Giovanni De Micheli, Donatella Sciuto...