1093 search results - page 15 / 219 » Verifying VLSI Circuits |
CCL
1994
Springer
13 years 11 months ago
1994
Springer
Abstract: This paper describes the application of CLP (constraint logic programming) to several digital circuit design problems. It is shown that logic programming together with ef...
ISVLSI
2002
IEEE
14 years 13 days ago
2002
IEEE
Timed Shannon circuits have been proposed as a synthesis approach for a low power optimization technique at the logic level since overall circuit switching probabilities may be re...
CLEIEJ
2010
13 years 4 months ago
2010
A 3D circuit is the stacking of regular 2D circuits. The advances on the fabrication and packaging technologies allowed interconnecting stacked 2D circuits by using 3D vias. Howeve...
GLVLSI
1998
IEEE
13 years 11 months ago
1998
IEEE
The dynamic and short-circuit power consumption of a complementary metal
TIM
2010
13 years 2 months ago
2010
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...