1093 search results - page 184 / 219 » Verifying VLSI Circuits |
VLSID
2009
IEEE
14 years 9 months ago
2009
IEEE
The current paradigm of using Cu interconnects for on-chip global communication is rapidly becoming a serious performance bottleneck in ultra-deep submicron (UDSM) technologies. C...
VLSID
2008
IEEE
14 years 9 months ago
2008
IEEE
Abstract-- With the continuous downscaling of CMOS technologies, the reliability has become a major bottleneck in the evolution of the next generation systems. Technology trends su...
VLSID
2007
IEEE
14 years 9 months ago
2007
IEEE
Leakage power is becoming a dominant contributor to the total power consumption and dual-Vth assignment is an efficient technique to decrease leakage power, for which effective de...
VLSID
2007
IEEE
14 years 9 months ago
2007
IEEE
Device scaling such as reduced oxide thickness and high electric field has given rise to various reliability concerns. One such growing issue of concern is the degradation of PMOS...
VLSID
2005
IEEE
14 years 9 months ago
2005
IEEE
Two Simple structures of low-power Dual-edge triggered Static Pulsed Flip-Flops (DSPFF) are presented in this paper. They are composed of a dualedge pulse generator and a static f...