1093 search results - page 196 / 219 » Verifying VLSI Circuits |
ENGL
2008
13 years 7 months ago
2008
This paper discusses novel dedicated hardware architecture for hybrid optimization based on Genetic algorithm (GA) and Simulated Annealing (SA). The proposed architecture achieves ...
CSUR
2006
13 years 7 months ago
2006
resents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. ...
TVLSI
2008
13 years 7 months ago
2008
-- Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicron regime. As a result, reducing the subthreshold a...
TCAD
2002
13 years 7 months ago
2002
In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provi...
DSD
2010
IEEE
13 years 5 months ago
2010
IEEE
We present a high-level synthesis flow for mapping an algorithm description (in C) to a provably equivalent registertransfer level (RTL) description of hardware. This flow uses an ...