Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology

-- Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicron regime. As a result, reducing the subthreshold and tunneling gate leakage currents has become one of the most important criteria in the design of VLSI circuits. This paper presents a method based on dual-Vt and dual-Tox assignment to reduce the total leakage power dissipation of SRAMs while maintaining their performance. The proposed method is based on the observation that read and write delays of a memory cell in an SRAM block depend on the physical distance of the cell from the sense amplifier and the decoder. Thus, the idea is to deploy different configurations of six-transistor SRAM cells corresponding to different threshold voltage and oxide thickness assignments for the transistors. Unlike other techniques for lowleakage SRAM design, the proposed technique incurs neither area nor delay overhead. In addition, it results in a minor change in the SRAM d...

• Type: Journal
• Year: 2008
• Where: TVLSI
• Authors: Behnam Amelifard, Farzan Fallah, Massoud Pedram
• Keywords: Leakage Power Dissipation, Oxide Thickness, Threshold Voltage, TVLSI 2008