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» Verifying VLSI Circuits
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SBCCI
2006
ACM
139views VLSI» more  SBCCI 2006»
14 years 1 months ago
Infrastructure for dynamic reconfigurable systems: choices and trade-offs
Platform-based design is a method to implement complex SoCs, avoiding chip design from scratch. A promising evolution of platform-based design are MPSoC. Such generic architecture...
Leandro Möller, Rafael Soares, Ewerson Carval...
SBCCI
2005
ACM
98views VLSI» more  SBCCI 2005»
14 years 1 months ago
Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation
This work addresses the problem of application mapping in networks-on-chip (NoCs). It explores the importance of characterizing network traffic to effectively predict NoC energy c...
José Carlos S. Palma, César A. M. Ma...
SBCCI
2005
ACM
114views VLSI» more  SBCCI 2005»
14 years 1 months ago
Traffic generation and performance evaluation for mesh-based NoCs
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these ...
Leonel Tedesco, Aline Mello, Diego Garibotti, Ney ...
GLVLSI
2003
IEEE
119views VLSI» more  GLVLSI 2003»
14 years 25 days ago
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
ISPD
2003
ACM
110views Hardware» more  ISPD 2003»
14 years 24 days ago
Explicit gate delay model for timing evaluation
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxi...