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» Verifying VLSI Circuits
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ISPD
2005
ACM
174views Hardware» more  ISPD 2005»
14 years 2 months ago
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design
In this paper, we present a very fast and accurate rectilinear Steiner minimal tree (RSMT)1 algorithm called FLUTE. The algorithm is an extension of the wirelength estimation appr...
Chris C. N. Chu, Yiu-Chung Wong
ISQED
2007
IEEE
187views Hardware» more  ISQED 2007»
14 years 3 months ago
High-Frequency-Measurement-Based Frequency-Variant Transmission Line Characterization and Circuit Modeling for Accurate Signal I
Novel experimental characterization method and circuit modeling for frequency-variant transmission lines are presented. Experimental test patterns are designed and fabricated by u...
Hyunsik Kim, Yungseon Eo
KDD
2000
ACM
211views Data Mining» more  KDD 2000»
14 years 11 days ago
Mining IC test data to optimize VLSI testing
We describe an application of data mining and decision analysis to the problem of die-level functional test in integrated circuit manufacturing. Integrated circuits are fabricated...
Tony Fountain, Thomas G. Dietterich, Bill Sudyka
DAC
2010
ACM
13 years 10 months ago
Detecting tangled logic structures in VLSI netlists
This work proposes a new problem of identifying large and tangled logic structures in a synthesized netlist. Large groups of cells that are highly interconnected to each other can...
Tanuj Jindal, Charles J. Alpert, Jiang Hu, Zhuo Li...
IJNS
2000
130views more  IJNS 2000»
13 years 8 months ago
A Programmable VLSI Filter Architecture for Application in Real-Time Vision Processing Systems
An architecture is proposed for the realization of real-time edge-extraction filtering operation in an Address-Event-Representation (AER) vision system. Furthermore, the approach ...
Teresa Serrano-Gotarredona, Andreas G. Andreou, Be...