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» Verifying VLSI Circuits
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GLVLSI
2008
IEEE
204views VLSI» more  GLVLSI 2008»
14 years 4 months ago
NBTI resilient circuits using adaptive body biasing
Reliability has become a practical concern in today’s VLSI design with advanced technologies. In-situ sensors have been proposed for reliability monitoring to provide advance wa...
Zhenyu Qi, Mircea R. Stan
ICCAD
2003
IEEE
114views Hardware» more  ICCAD 2003»
14 years 6 months ago
A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning
As the size and complexity of VLSI circuits increase, the need for faster floorplanning algorithms also grows. In this work we introduce Traffic, a new method for creating wire- a...
Peter G. Sassone, Sung Kyu Lim
GLVLSI
2007
IEEE
115views VLSI» more  GLVLSI 2007»
14 years 4 months ago
Novel architectures for efficient (m, n) parallel counters
Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3, 2), (7, 3...
Sreehari Veeramachaneni, Lingamneni Avinash, Kirth...
GLVLSI
2005
IEEE
158views VLSI» more  GLVLSI 2005»
14 years 3 months ago
Quantum-dot cellular automata SPICE macro model
This paper describes a SPICE model development methodology for Quantum-Dot Cellular Automata (QCA) cells and presents a SPICE model for QCA cells. The model is validated by simula...
Rui Tang, Fengming Zhang, Yong-Bin Kim
GLVLSI
2003
IEEE
185views VLSI» more  GLVLSI 2003»
14 years 3 months ago
Shielding effect of on-chip interconnect inductance
—Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effectiv...
Magdy A. El-Moursy, Eby G. Friedman