1093 search results - page 65 / 219 » Verifying VLSI Circuits |
GLVLSI
1999
IEEE
14 years 2 months ago
1999
IEEE
Despite the seemingly endless upwards spiral of modern VLSI technology, many experts are predicting a hard wall for CMOS in about a decade. Given this, researchers continue to loo...
VLSID
2002
IEEE
14 years 10 months ago
2002
IEEE
Our target is automation of analog circuit's layout, which is a bottleneck in mixed-signal's design. We formulate the layout explicitly considering manufacturing process...
VTS
2002
IEEE
14 years 2 months ago
2002
IEEE
We present a test methodology to allow testing high-speed circuits with low-speed ATEs. The basic strategy is adding an interface circuit to partially supply test data, coordinate...
DAC
2005
ACM
13 years 12 months ago
2005
ACM
We propose a normalization technique for verifying arithmetic circuits in a bounded model checking environment. Our technique operates on the arithmetic bit level (ABL) descriptio...
GLVLSI
2005
IEEE
14 years 3 months ago
2005
IEEE
In this paper we develop a theory of equivalence checking (EC) and logic synthesis of circuits with a common specification (CS). We show that two combinational circuits N1, N2 have...