1093 search results - page 69 / 219 » Verifying VLSI Circuits |
DFT
1999
IEEE
14 years 2 months ago
1999
IEEE
In the last decade, researchers have devoted increasing efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption durin...
VLSID
2002
IEEE
14 years 10 months ago
2002
IEEE
As a basic cell of arithmetic circuits, a one-bit full adder and a counter are usually used. Minimizing power consumption of these components is a key issue for low-power circuit ...
DFT
2008
IEEE
14 years 4 months ago
2008
IEEE
The paper presents a new technique for designing a concurrently checking combinational circuit. The technique is based on partitioning the circuit into two independent sub-circuit...
GECCO
2004
Springer
14 years 3 months ago
2004
Springer
We propose a hybrid genetic algorithm for partitioning a VLSI circuit graph into two disjoint graphs of minimum cut size. The algorithm includes a local optimization heuristic whic...
FCCM
2007
IEEE
14 years 4 months ago
2007
IEEE
— Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness. This p...