1093 search results - page 76 / 219 » Verifying VLSI Circuits |
FCCM
2004
IEEE
14 years 1 months ago
2004
IEEE
This paper describes the package of test bench code required to verify the Algotronix' AES IP Core. Several authors (see the references in [3]) have published papers detailing...
ICCAD
2007
IEEE
14 years 7 months ago
2007
IEEE
—We present an implementation of an algorithm for constructing provably fast circuits for a class of Boolean functions with input signals that have individual starting times. We ...
ISCAS
2006
IEEE
14 years 4 months ago
2006
IEEE
— This paper presents some circuitry for use within a visual-processing depth-recovery algorithm based upon spike timing. The accuracy of the depth calculation relies on a predic...
GLVLSI
2010
IEEE
14 years 3 months ago
2010
IEEE
We present the architecture of a new Ordered Binary Decision Diagram library that is designed from the ground up to be space efficient. The main novelty lies in the library’s no...
GLVLSI
2000
IEEE
14 years 2 months ago
2000
IEEE
: We propose a novel evolutionary approach to the problem of timing-driven FPGA placement. The method used is evolutionary programming (EP) with incremental position encoded in the...