1093 search results - page 94 / 219 » Verifying VLSI Circuits |
PDP
2003
IEEE
14 years 3 months ago
2003
IEEE
As general-purpose parallel computers are increasingly being used to speed up different VLSI applications, the development of parallel algorithms for circuit testing, logic minimi...
KBSE
2007
IEEE
14 years 4 months ago
2007
IEEE
A number of researchers have proposed the use of Boolean satisfiability solvers for verifying C programs. They encode correctness checks as Boolean formulas using finitization: ...
CAV
1994
Springer
14 years 2 months ago
1994
Springer
This paper presents a new formalism and a new algorithm for verifying timed circuits. The formalism, called orbital nets, allows hierarchical verification based on abehavioralseman...
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
The Monte Carlo (MC) simulation is a well-known solution to the statistical analysis of analog circuits in the presence of device mismatch. Despite MC's superior accuracy comp...
ASPDAC
2007
ACM
14 years 2 months ago
2007
ACM
-- Analog circuit sizing under process/parameter variations is formulated as a mini-max geometric programming problem. To tackle such problem, we present a new method that combines...