222 search results - page 4 / 45 » Verifying an Arbiter Circuit |
CAV
1991
Springer
13 years 11 months ago
1991
Springer
CJ
2010
13 years 8 months ago
2010
rder logic (HOL) theorem prover. The high ability of abstraction in the HOL verification system allows its use for the verification task over the whole design path of the circuit, ...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
Building fully synchronous VLSI circuits is becoming less viable as circuit geometries evolve. However, before the adoption of purely asynchronous strategies in VLSI design, globa...
DATE
2002
IEEE
14 years 26 days ago
2002
IEEE
This paper addresses verifying the timing of circuits containing level-sensitive latches in the presence of cross talk. We show that three consecutive periodic occurrences of the ...
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
To handle today’s complexity, modern circuits and systems be specified at a high level of abstraction. Recently, SystemC has been proposed as a language that allows a fast on o...