Sciweavers

1508 search results - page 255 / 302
» Versatile Processor Design for Efficiency and High Performan...
Sort
View
MICRO
2006
IEEE
144views Hardware» more  MICRO 2006»
14 years 2 months ago
Die Stacking (3D) Microarchitecture
3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die ...
Bryan Black, Murali Annavaram, Ned Brekelbaum, Joh...
ASPLOS
2006
ACM
14 years 2 months ago
Ultra low-cost defect protection for microprocessor pipelines
The sustained push toward smaller and smaller technology sizes has reached a point where device reliability has moved to the forefront of concerns for next-generation designs. Sil...
Smitha Shyam, Kypros Constantinides, Sujay Phadke,...
USENIX
1994
13 years 10 months ago
Reducing File System Latency using a Predictive Approach
Despite impressive advances in file system throughput resulting from technologies such as high-bandwidth networks and disk arrays, file system latency has not improved and in many...
Jim Griffioen, Randy Appleton
ACMMSP
2004
ACM
92views Hardware» more  ACMMSP 2004»
14 years 2 months ago
Instruction combining for coalescing memory accesses using global code motion
Instruction combining is an optimization to replace a sequence of instructions with a more efficient instruction yielding the same result in a fewer machine cycles. When we use it...
Motohiro Kawahito, Hideaki Komatsu, Toshio Nakatan...
DAC
2000
ACM
14 years 9 months ago
High-level simulation of substrate noise generation including power supply noise coupling
Substrate noise caused by large digital circuits will degrade the performance of analog circuits located on the same substrate. To simulate this performance degradation, the total...
Marc van Heijningen, Mustafa Badaroglu, Sté...