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PC
2007
161views Management» more  PC 2007»
13 years 8 months ago
High performance combinatorial algorithm design on the Cell Broadband Engine processor
The Sony–Toshiba–IBM Cell Broadband Engine (Cell/B.E.) is a heterogeneous multicore architecture that consists of a traditional microprocessor (PPE) with eight SIMD co-process...
David A. Bader, Virat Agarwal, Kamesh Madduri, Seu...
ARCS
2004
Springer
14 years 2 months ago
Modelling Cryptonite - On the Design of a Programmable High-Performance Crypto Processor
: Cryptographic algorithms – even when designed for easy implementability on general purpose architectures – still show a huge performance gap between implementations in softwa...
Rainer Buchty
ISCC
2005
IEEE
119views Communications» more  ISCC 2005»
14 years 2 months ago
A Systematic Approach to Building High Performance Software-Based CRC Generators
—A framework for designing a family of novel fast CRC generation algorithms is presented. Our algorithms can ideally read arbitrarily large amounts of data at a time, while optim...
Michael E. Kounavis, Frank L. Berry
DATE
2006
IEEE
127views Hardware» more  DATE 2006»
14 years 2 months ago
ASIP architecture for multi-standard wireless terminals
This paper presents the Block Processing Engine (BPE), an Application Specific Instruction-Set Processor (ASIP) explicitly designed for the implementation of multistandard wireles...
Daniele Lo Iacono, J. Zory, Ettore Messina, N. Pia...
JPDC
2006
141views more  JPDC 2006»
13 years 8 months ago
M-TREE: A high efficiency security architecture for protecting integrity and privacy of software
Secure processor architectures enable new sets of applications such as commercial grid computing, software copy protection and secure mobile agents by providing secure computing e...
Chenghuai Lu, Tao Zhang, Weidong Shi, Hsien-Hsin S...