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» Very Compact FPGA Implementation of the AES Algorithm
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FPGA
1998
ACM
153views FPGA» more  FPGA 1998»
13 years 11 months ago
SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays
It has become clear that large embedded con gurable memory arrays will be essential in future FPGAs. Embedded arrays provide high-density high-speed implementations of the storage...
Steven J. E. Wilton
FPGA
2001
ACM
152views FPGA» more  FPGA 2001»
13 years 12 months ago
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
Jörg Ritter, Paul Molitor
WISA
2004
Springer
14 years 22 days ago
Hyperelliptic Curve Coprocessors on a FPGA
Abstract. Cryptographic algorithms are used in a large variety of different applications to ensure security services. It is, thus, very interesting to investigate various implement...
Howon Kim, Thomas J. Wollinger, YongJe Choi, Kyoil...
FPGA
2000
ACM
109views FPGA» more  FPGA 2000»
13 years 11 months ago
Heterogeneous technology mapping for FPGAs with dual-port embedded memory arrays
It has become clear that on-chip storage is an essential component of high-density FPGAs. These arrays were originally intended to implement storage, but recent work has shown tha...
Steven J. E. Wilton
FPGA
1999
ACM
139views FPGA» more  FPGA 1999»
13 years 11 months ago
Trading Quality for Compile Time: Ultra-Fast Placement for FPGAs
The demand for high-speed FPGA compilation tools has occurred for three reasons: first, as FPGA device capacity has grown, the computation time devoted to placement and routing h...
Yaska Sankar, Jonathan Rose