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GLVLSI
2007
IEEE
187views VLSI» more  GLVLSI 2007»
14 years 1 months ago
DAG based library-free technology mapping
This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through t...
Felipe S. Marques, Leomar S. da Rosa Jr., Renato P...
ISLPED
2004
ACM
153views Hardware» more  ISLPED 2004»
14 years 1 months ago
Any-time probabilistic switching model using bayesian networks
Modeling and estimation of switching activities remain to be important problems in low-power design and fault analysis. A probabilistic Bayesian Network based switching model can ...
Shiva Shankar Ramani, Sanjukta Bhanja
ISCAS
2003
IEEE
82views Hardware» more  ISCAS 2003»
14 years 26 days ago
A hyperchaotic circuit family including a dependent switched capacitor
This paper studies simple hyperchaotic circuits consisting of one linear 3-port voltage-controlled current source (ab. VCCS), two linear capacitors and one dependent switched capa...
Yusuke Takahashi, Hidehiro Nakano, Toshimichi Sait...
ICCAD
1994
IEEE
139views Hardware» more  ICCAD 1994»
13 years 11 months ago
Switching activity analysis considering spatiotemporal correlations
This work presents techniques for computing the switching activities of all circuit nodes under pseudorandom or biased input sequences and assuming a zero delay mode of operation....
Radu Marculescu, Diana Marculescu, Massoud Pedram
ENGL
2007
180views more  ENGL 2007»
13 years 7 months ago
Reordering Algorithm for Minimizing Test Power in VLSI Circuits
— Power consumption has become a crucial concern in Built In Self Test (BIST) due to the switching activity in the circuit under test(CUT). In this paper we present a novel metho...
K. Paramasivam, K. Gunavathi