This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through t...
Felipe S. Marques, Leomar S. da Rosa Jr., Renato P...
Modeling and estimation of switching activities remain to be important problems in low-power design and fault analysis. A probabilistic Bayesian Network based switching model can ...
This paper studies simple hyperchaotic circuits consisting of one linear 3-port voltage-controlled current source (ab. VCCS), two linear capacitors and one dependent switched capa...
This work presents techniques for computing the switching activities of all circuit nodes under pseudorandom or biased input sequences and assuming a zero delay mode of operation....
— Power consumption has become a crucial concern in Built In Self Test (BIST) due to the switching activity in the circuit under test(CUT). In this paper we present a novel metho...