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ICDCS
2010
IEEE
13 years 11 months ago
A New Buffer Cache Design Exploiting Both Temporal and Content Localities
: This paper presents a Least Popularly Used buffer cache algorithm to exploit both temporal locality and content locality of I/O requests. Popular data blocks are selected as refe...
Jin Ren, Qing Yang
TPDS
2010
125views more  TPDS 2010»
13 years 2 months ago
Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherence Level
The importance of transient faults is predicted to grow due to current technology trends of increased scale of integration. One of the components that will be significantly affecte...
Ricardo Fernández Pascual, José M. G...
DSN
2008
IEEE
14 years 2 months ago
A fault-tolerant directory-based cache coherence protocol for CMP architectures
Current technology trends of increased scale of integration are pushing CMOS technology into the deepsubmicron domain, enabling the creation of chips with a significantly greater...
Ricardo Fernández Pascual, José M. G...
CTRSA
2006
Springer
146views Cryptology» more  CTRSA 2006»
13 years 11 months ago
Cache Attacks and Countermeasures: The Case of AES
We describe several software side-channel attacks based on inter-process leakage through the state of the CPU's memory cache. This leakage reveals memory access patterns, whic...
Dag Arne Osvik, Adi Shamir, Eran Tromer
WSC
1997
13 years 9 months ago
Efficient Instruction Cache Simulation and Execution Profiling with a Threaded-Code Interpreter
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
Peter S. Magnusson