2811 search results - page 96 / 563 » Virtue: Performance Visualization of Parallel and Distribute... |
IPPS
1998
IEEE
14 years 1 months ago
1998
IEEE
The Loop-Level Process Control LLPC policy 9 dynamically adjusts the number of threads an application is allowed to execute based on the application's available parallelism a...
IPPS
2009
IEEE
14 years 3 months ago
2009
IEEE
In this paper we discuss our initial experiences adapting OpenMP to enable it to serve as a programming model for high performance embedded systems. A high-level programming model...
IPPS
2000
IEEE
14 years 1 months ago
2000
IEEE
Abstract. Computer vision is a challenging data intensive application. Currently, superscalar architectures dominate the processor marketplace. As more transistors become available...
IPPS
2010
IEEE
13 years 6 months ago
2010
IEEE
The memory hierarchy of most multicore systems contains one or more levels of cache that is shared among multiple cores. The shared-cache architecture presents many opportunities f...
BMCBI
2008
13 years 9 months ago
2008
Background: Innumerable biological investigations require comparing collections of molecules, cells or organisms to one another with respect to one or more of their properties. Al...