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» Visualisation of Large and Complex Networks Using PolyPlane
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SLIP
2006
ACM
14 years 2 months ago
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
— The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable ha...
Jin Guo, Antonis Papanikolaou, Pol Marchal, Franck...
POLICY
2001
Springer
14 years 1 months ago
The Ponder Policy Specification Language
The Ponder language provides a common means of specifying security policies that map onto various access control implementation mechanisms for firewalls, operating systems, databas...
Nicodemos Damianou, Naranker Dulay, Emil Lupu, Mor...
IROS
2007
IEEE
97views Robotics» more  IROS 2007»
14 years 2 months ago
Meld: A declarative approach to programming ensembles
Abstract— This paper presents Meld, a programming language for modular robots, i.e., for independently executing robots where inter-robot communication is limited to immediate ne...
Michael P. Ashley-Rollman, Seth Copen Goldstein, P...
EGC
2005
Springer
14 years 2 months ago
A Monitoring Architecture for Control Grids
Abstract. Monitoring systems are nowadays ubiquitous in complex environments, such as Grids. Their use is fundamental for performance evaluation, problem spotting, advanced debuggi...
Alexandru Iosup, Nicolae Tapus, Stéphane Vi...
DATE
2005
IEEE
107views Hardware» more  DATE 2005»
14 years 2 months ago
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique
Complex applications implemented as Systems on Chip (SoCs) demand extensive use of system level modeling and validation. Their implementation gathers a large number of complex IP ...
César A. M. Marcon, Ney Laert Vilar Calazan...