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» Visualization of SystemC Designs
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DATE
2005
IEEE
130views Hardware» more  DATE 2005»
15 years 8 months ago
Design for Verification of SystemC Transaction Level Models
Ali Habibi, Sofiène Tahar
DELTA
2006
IEEE
15 years 8 months ago
Static Code Analysis of Functional Descriptions in SystemC
The co-design of hardware and software systems with object oriented design languages like SystemC has become very popular. Static analysis of those descriptions allows to conduct ...
Martin Holzer 0002, Markus Rupp
ISVLSI
2007
IEEE
230views VLSI» more  ISVLSI 2007»
15 years 8 months ago
A Methodology and Toolset to Enable SystemC and VHDL Co-simulation
The new design challenges imposed by the increasing difficulties of today’s electronic systems obligated designers to develop new methodologies. System-level design and Platfor...
Richard Maciel, Bruno Albertini, Sandro Rigo, Guid...