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DATE
2010
IEEE
124views Hardware» more  DATE 2010»
14 years 23 days ago
Control network generator for latency insensitive designs
—Creating latency insensitive or asynchronous designs from clocked designs has potential benefits of increased modularity and robustness to variations. Several transformations h...
Eliyah Kilada, Kenneth S. Stevens
EUC
2004
Springer
13 years 11 months ago
Efficient Scheduling for Design Exploration with Imprecise Latency and Register Constraints
In archiectural synthesis, scheduling and resource allocation are important steps. During the early stage of the design, imprecise information is unavoidable. Under the imprecise ...
Chantana Chantrapornchai, Wanlop Surakumpolthorn, ...
MICRO
1998
IEEE
89views Hardware» more  MICRO 1998»
13 years 12 months ago
Load Latency Tolerance in Dynamically Scheduled Processors
This paper provides quantitative measurements of load latency tolerance in a dynamically scheduled processor. To determine the latency tolerance of each memory load operation, our...
Srikanth T. Srinivasan, Alvin R. Lebeck
EICS
2009
ACM
14 years 2 months ago
The tradeoff between spatial jitter and latency in pointing tasks
Interactive computing systems frequently use pointing as an input modality, while also supporting other forms of input such as alphanumeric, voice, gesture, and force. We focus on...
Andriy Pavlovych, Wolfgang Stürzlinger
MOBICOM
2003
ACM
14 years 27 days ago
A comparison of mechanisms for improving mobile IP handoff latency for end-to-end TCP
Handoff latency results in packet losses and severe End-to-End TCP performance degradation as TCP, perceiving these losses as congestion, causes source throttling or retransmissio...
Robert Hsieh, Aruna Seneviratne