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» Walkers on the Cycle and the Grid
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ICPP
2000
IEEE
13 years 12 months ago
Multilayer VLSI Layout for Interconnection Networks
Current VLSI technology allows more than two wiring layers and the number is expected to rise in future. In this paper, we show that, by designing VLSI layouts directly for an L-l...
Chi-Hsiang Yeh, Emmanouel A. Varvarigos, Behrooz P...
HCW
1999
IEEE
13 years 11 months ago
A Unified Resource Scheduling Framework for Heterogeneous Computing Environments
A major challenge in Metacomputing Systems (Computational Grids) is to effectively use their shared resources, such as compute cycles, memory, communication network, and data repo...
Ammar H. Alhusaini, Viktor K. Prasanna, Cauligi S....
VIS
2006
IEEE
214views Visualization» more  VIS 2006»
14 years 8 months ago
Hub-based Simulation and Graphics Hardware Accelerated Visualization for Nanotechnology Applications
The Network for Computational Nanotechnology (NCN) has developed a science gateway at nanoHUB.org for nanotechnology education and research. Remote users can browse through online...
Wei Qiao, Michael McLennan, Rick Kennell, David...
DSRT
2008
IEEE
14 years 1 months ago
Interfacing and Coordination for a DEVS Simulation Protocol Standard
The DEVS formalism has been adopted and developed independently by many research teams, which led to various DEVS implementation versions. Consequently, different DEVS implementat...
Khaldoon Al-Zoubi, Gabriel A. Wainer
ISCA
2002
IEEE
91views Hardware» more  ISCA 2002»
14 years 11 days ago
Slack: Maximizing Performance Under Technological Constraints
Many emerging processor microarchitectures seek to manage technological constraints (e.g., wire delay, power, and circuit complexity) by resorting to nonuniform designs that provi...
Brian A. Fields, Rastislav Bodík, Mark D. H...