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FCCM
1997
IEEE
103views VLSI» more  FCCM 1997»
13 years 12 months ago
An FPGA architecture for DRAM-based systolic computations
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
Norman Margolus
FAST
2004
13 years 9 months ago
Tracefs: A File System to Trace Them All
File system traces have been used for years to analyze user behavior and system software behavior, leading to advances in file system and storage technologies. Existing traces, ho...
Akshat Aranya, Charles P. Wright, Erez Zadok
JSA
2008
94views more  JSA 2008»
13 years 7 months ago
Energy reduction through crosstalk avoidance coding in networks on chip
Commercial designs are currently integrating from 10 to 100 embedded processors in a single system on chip (SoC) and the number is likely to increase significantly in the near fut...
Partha Pratim Pande, Amlan Ganguly, Haibo Zhu, Cri...
INFOCOM
2010
IEEE
13 years 6 months ago
Reliable Adaptive Multipath Provisioning with Bandwidth and Differential Delay Constraints
Abstract— Robustness and reliability are critical issues in network management. To provide resiliency, a popular protection scheme against network failures is the simultaneous ro...
Weiyi Zhang, Jian Tang, Chonggang Wang, Shanaka de...
CVPR
1999
IEEE
14 years 9 months ago
Bayesian Multi-Camera Surveillance
The task of multi-camera surveillance is to reconstruct the paths taken by all moving objects that are temporarily visible from multiple non-overlapping cameras. We present a Baye...
Vera Kettnaker, Ramin Zabih