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DAC
2006
ACM
14 years 8 months ago
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several othe...
Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sh...
ICS
2010
Tsinghua U.
13 years 10 months ago
The auction: optimizing banks usage in Non-Uniform Cache Architectures
The growing influence of wire delay in cache design has meant that access latencies to last-level cache banks are no longer constant. Non-Uniform Cache Architectures (NUCAs) have ...
Javier Lira, Carlos Molina, Antonio Gonzále...
USENIX
2008
13 years 10 months ago
Vx32: Lightweight User-level Sandboxing on the x86
Code sandboxing is useful for many purposes, but most sandboxing techniques require kernel modifications, do not completely isolate guest code, or incur substantial performance co...
Bryan Ford, Russ Cox
ICCD
2008
IEEE
117views Hardware» more  ICCD 2008»
14 years 4 months ago
Two dimensional highly associative level-two cache design
High associativity is important for level-two cache designs [9]. Implementing CAM-based Highly Associative Caches (CAM-HAC), however, is both costly in hardware and exhibits poor s...
Chuanjun Zhang, Bing Xue
ICPR
2006
IEEE
14 years 8 months ago
Estimating Geospatial Trajectory of a Moving Camera
This paper proposes a novel method for estimating the geospatial trajectory of a moving camera. The proposed method uses a set of reference images with known GPS (global positioni...
Asaad Hakeem, Mubarak Shah, Rita Cucchiara, Robert...