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SBCCI
2005
ACM
114views VLSI» more  SBCCI 2005»
15 years 7 months ago
Traffic generation and performance evaluation for mesh-based NoCs
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these ...
Leonel Tedesco, Aline Mello, Diego Garibotti, Ney ...
106
Voted
SLIP
2005
ACM
15 years 7 months ago
Congestion prediction in early stages
Routability optimization has become a major concern in the physical design cycle of VLSI circuits. Due to the recent advances in VLSI technology, interconnect has become a dominan...
Chiu-Wing Sham, Evangeline F. Y. Young
104
Voted
IPPS
1999
IEEE
15 years 6 months ago
Scalable Hardware-Algorithms for Binary Prefix Sums
Abstract. Themain contributionof thiswork isto propose a numberof broadcastefficient VLSI architectures for computing the sum and the prefix sums of a w k-bit, k 2, binary sequenc...
Rong Lin, Koji Nakano, Stephan Olariu, Maria Crist...
113
Voted
WWW
2002
ACM
16 years 2 months ago
A web-based resource migration protocol using WebDAV
The web's hyperlinks are notoriously brittle, and break whenever a resource migrates. One solution to this problem is a transparent resource migration mechanism, which separa...
Michael P. Evans, Steven Furnell
95
Voted
DAC
2007
ACM
16 years 3 months ago
TROY: Track Router with Yield-driven Wire Planning
In this paper, we propose TROY, the first track router with yield-driven wire planning to optimize yield loss due to random defects. As the probability of failure (POF) computed f...
Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan