This paper proposes a test architecture aimed at reducing test time of distributed small embedded SRAMs (eSRAMs). This architecture improves the one proposed in [4, 5]. The improv...
CAD tools have become more and more important for integrated circuit (IC) design since a complicated system can be designed into a single chip, called system-on-a-chip (SOC), in w...
Yang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu...
The task of computingbinary prefix sums (BPS, for short) arises, for example, in expression evaluation, data and storage compaction, and routing. This paper describes a scalable V...
Rong Lin, Koji Nakano, Stephan Olariu, Maria Crist...
A sensitivity analysis of resonant H-tree clock distribution networks is presented in this paper for a TSMC 0.18 μm CMOS technology. The analysis focuses on the effect of the dri...
In this paper, we present a new statistical technique for estimation of average power dissipation in digital circuits. Present statistical techniques estimate the average power ba...