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DFT
2004
IEEE
101views VLSI» more  DFT 2004»
14 years 1 months ago
Designs for Reducing Test Time of Distributed Small Embedded SRAMs
This paper proposes a test architecture aimed at reducing test time of distributed small embedded SRAMs (eSRAMs). This architecture improves the one proposed in [4, 5]. The improv...
Baosheng Wang, Yuejian Wu, André Ivanov
ASAP
2005
IEEE
135views Hardware» more  ASAP 2005»
14 years 3 months ago
Via-Aware Global Routing for Good VLSI Manufacturability and High Yield
CAD tools have become more and more important for integrated circuit (IC) design since a complicated system can be designed into a single chip, called system-on-a-chip (SOC), in w...
Yang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu...
IPPS
1998
IEEE
14 years 2 months ago
A Scalable VLSI Architecture for Binary Prefix Sums
The task of computingbinary prefix sums (BPS, for short) arises, for example, in expression evaluation, data and storage compaction, and routing. This paper describes a scalable V...
Rong Lin, Koji Nakano, Stephan Olariu, Maria Crist...
GLVLSI
2006
IEEE
120views VLSI» more  GLVLSI 2006»
14 years 3 months ago
Sensitivity evaluation of global resonant H-tree clock distribution networks
A sensitivity analysis of resonant H-tree clock distribution networks is presented in this paper for a TSMC 0.18 μm CMOS technology. The analysis focuses on the effect of the dri...
Jonathan Rosenfeld, Eby G. Friedman
ISLPED
1996
ACM
110views Hardware» more  ISLPED 1996»
14 years 1 months ago
Statistical estimation of average power dissipation in CMOS VLSI circuits using nonparametric techniques
In this paper, we present a new statistical technique for estimation of average power dissipation in digital circuits. Present statistical techniques estimate the average power ba...
Li-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang