In this paper, we present a syntax-directed termination and reduction checker for higher-order logic programs. The reduction checker verifies parametric higher-order subterm orderi...
Hybrid logic nets contain nodes that exhibit recurrent characteristics, in that a node output shows temporal tendencies even when the inputs are constant (Al-Dabass et al. 1999a a...
David Al-Dabass, David J. Evans, Siva Sivayoganath...
Reversible logic design has become one of the promising research directions in low power dissipating circuit design in the past few years and has found its application in low power...
Md. Saiful Islam 0003, Muhammad Mahbubur Rahman, Z...
This paper presents a concurrent error detection technique targeted towards control logic in a processor with emphasis on low area overhead. Rather than detect all modeled transie...
Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srin...
In this paper, we consider addressable procedures with DNA strands for logic and arithmetic operations. Using a theoretical model for DNA computing, we first show a DNA represent...