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VTS
2005
IEEE
89views Hardware» more  VTS 2005»
14 years 1 months ago
Synthesis of Low Power CED Circuits Based on Parity Codes
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
Shalini Ghosh, Sugato Basu, Nur A. Touba
ICASSP
2011
IEEE
12 years 11 months ago
Slice error concealment based on size-adaptive SSIM matching and motion vector outlier rejection
Consecutive corrupted MBs or slice errors are commonly seen in modern video transmission systems. Temporal error concealment is an effective approach to reduce the impact of error...
Hai Gao, Jo Yew Tham, Wei Siong Lee, Kwong Huang G...
MICRO
2010
IEEE
202views Hardware» more  MICRO 2010»
13 years 2 months ago
Hardware Support for Relaxed Concurrency Control in Transactional Memory
Today's transactional memory systems implement the two-phase-locking (2PL) algorithm which aborts transactions every time a conflict happens. 2PL is a simple algorithm that pr...
Utku Aydonat, Tarek S. Abdelrahman
ICIP
2008
IEEE
14 years 9 months ago
Estimation of optimum coding redundancy and frequency domain analysis of attacks for YASS - a randomized block based hiding sche
Our recently introduced JPEG steganographic method called Yet Another Steganographic Scheme (YASS) can resist blind steganalysis by embedding data in the discrete cosine transform...
Anindya Sarkar, Lakshmanan Nataraj, B. S. Manjunat...
ICMCS
2006
IEEE
85views Multimedia» more  ICMCS 2006»
14 years 1 months ago
Prefilter Control Scheme for Low bitrate TV Distribution
In IP-based TV distribution, coding degradation is sometimes evident in critical scenes because the bit rate for compression is rather low. Prefiltering is an effective counterme...
Ryoichi Kawada, Atsushi Koike, Yasuyuki Nakajima