1485 search results - page 256 / 297 » Whole Program Paths |
ICCAD
2003
IEEE
14 years 27 days ago
2003
IEEE
This paper proposes for latency insensitive systems a performance optimization technique called channel buffer queue sizing, which is performed after relay station insertion in th...
PODS
2010
ACM
14 years 21 days ago
2010
ACM
A generalization from string to trees and from languages to translations is given of the classical result that any regular language can be learned from examples: it is shown that ...
ISCA
2002
IEEE
14 years 16 days ago
2002
IEEE
An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of th...
FPL
2001
Springer
14 years 3 days ago
2001
Springer
System and processor architectures depend on changes in technology. Looking ahead as die density and speed increase, power consumption and on chip interconnection delay become incr...
SIGGRAPH
2010
ACM
14 years 3 days ago
2010
ACM
We describe a framework for the automatic synthesis of biped locomotion controllers that adapt to uneven terrain at run-time. The framework consists of two components: a per-foots...