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ICALP
2005
Springer
14 years 7 days ago
Spatial Logics for Bigraphs
Bigraphs are emerging as a (meta-)model for concurrent calculi, like CCS, ambients, πcalculus, and Petri nets. They are built orthogonally on two structures: a hierarchical place...
Giovanni Conforti, Damiano Macedonio, Vladimiro Sa...
DEXAW
2003
IEEE
109views Database» more  DEXAW 2003»
14 years 19 hour ago
Metadata for Content Description In Legal Information
The paper describes the Jur-Wordnet (Jur-IWN) project, whose objective is an ontology-based extension to the legal domain of the Italian version of EuroWordNet. It aims at providi...
Maria-Teresa Sagri, Daniela Tiscornia
ICCAD
1999
IEEE
80views Hardware» more  ICCAD 1999»
13 years 11 months ago
What is the cost of delay insensitivity?
Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behaviour. Asynchronous spee...
Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, ...
DATE
2004
IEEE
126views Hardware» more  DATE 2004»
13 years 10 months ago
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
Latency-insensitive systems were recently proposed by Carloni et al. as a correct-by-construction methodology for single-clock system-on-a-chip (SoC) design using predesigned IP b...
Montek Singh, Michael Theobald
ACSD
2003
IEEE
105views Hardware» more  ACSD 2003»
13 years 10 months ago
Detecting State Coding Conflicts in STG Unfoldings Using SAT
Abstract. The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling...
Victor Khomenko, Maciej Koutny, Alexandre Yakovlev