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DATE
2005
IEEE
117views Hardware» more  DATE 2005»
14 years 1 months ago
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips
As Moore’s Law continues to fuel the ability to build ever increasingly complex system-on-chips (SoCs), achieving performance goals is rising as a critical challenge to completi...
Wolf-Dietrich Weber, Joe Chou, Ian Swarbrick, Drew...
IPPS
2005
IEEE
14 years 1 months ago
On the Scalability of Centralized Control
Scalability of clusters and MPPs is typically discussed in terms of limits on growth: something which grows at a rate of O(log p) (where p is the number of processors) is said to ...
Dror G. Feitelson
ISCAS
2005
IEEE
170views Hardware» more  ISCAS 2005»
14 years 1 months ago
Quantized LDPC decoder design for binary symmetric channels
Abstract— Binary Symmetric Channels (BSC) like the Interchip buses and the Intra-chip buses are gaining a lot of attention due to their widespread use with multimedia storage dev...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
IWANN
2005
Springer
14 years 1 months ago
CMOL CrossNets as Pattern Classifiers
This presentation has two goals: (i) to review the recently suggested concept of bio-inspired CrossNet architectures for future hybrid CMOL VLSI circuits and (ii) to present new re...
Jung Hoon Lee, Konstantin Likharev
VLDB
2004
ACM
122views Database» more  VLDB 2004»
14 years 1 months ago
Cache-Conscious Radix-Decluster Projections
As CPUs become more powerful with Moore’s law and memory latencies stay constant, the impact of the memory access performance bottleneck continues to grow on relational operator...
Stefan Manegold, Peter A. Boncz, Niels Nes