Sciweavers

11588 search results - page 174 / 2318
» Will They Like This
Sort
View
DATE
2009
IEEE
90views Hardware» more  DATE 2009»
14 years 5 months ago
Property analysis and design understanding
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
Ulrich Kühne, Daniel Große, Rolf Drechs...
DSD
2009
IEEE
124views Hardware» more  DSD 2009»
14 years 5 months ago
Network-on-Chip Architecture Exploration Framework
— In this paper, we present a novel framework for the automated generation of Network-on-Chips (NoC) architectures, that enables architecture exploration and optimization. The au...
Timo Schönwald, Jochen Zimmermann, Oliver Bri...
HPDC
2009
IEEE
14 years 5 months ago
Pluggable parallelisation
This paper presents the concept of pluggable parallelisation that allows scientists to develop “sequential like” codes that can take advantage of multi-core, cluster and grid ...
Rui C. Gonçalves, João Luís S...
ICC
2009
IEEE
173views Communications» more  ICC 2009»
14 years 5 months ago
Low-Complexity List-Based Frame Synchronization for LDPC Coded Transmission
Abstract—In this paper, we propose a simple and efficient twostage list synchronizer for frame synchronization of Low-Density Parity-Check (LDPC) coded data transmitted over the...
Cedomir Stefanovic, Dejan Vukobratovic, Dragana Ba...
ICDAR
2009
IEEE
14 years 5 months ago
A Survey of Techniques for Document and Archaeology Artefact Reconstruction
An automated assembling of shredded/torn documents (2D) or broken pottery (3D) will support philologists, archaeologists and forensic experts. An automated solution for this task ...
Florian Kleber, Robert Sablatnig