94 search results - page 9 / 19 » Wire width planning for interconnect performance optimizatio... |
TCAD
2002
13 years 7 months ago
2002
This paper introduces an accurate analysis of on-chip inductance effects for distributed interconnects that takes the effect of both the series resistance and the output parasitic ...
ICCAD
2000
IEEE
13 years 11 months ago
2000
IEEE
This paper presents an efficient method for optimizing power/ground (P/G) networks by widening wires and adding decoupling capacitors (decaps). It proposes a structured skeleton t...
IPPS
1998
IEEE
13 years 11 months ago
1998
IEEE
In this paper, the effect of switch design on the application performance of cache-coherent non-uniform memory access (CC-NUMA) multiprocessors is studied in detail. Wormhole rout...
DATE
2002
IEEE
14 years 9 days ago
2002
IEEE
We present a unified framework that considers flipflop and repeater insertion and the placement of flipflop/repeater blocks during RT or higher level design. We introduce the...
CONNECTION
2007
13 years 7 months ago
2007
In physical implementations of associative memory, wiring costs play a significant role in shaping patterns of connectivity. In this study of sparsely-connected associative memory...