564 search results - page 15 / 113 » Wireplanning in logic synthesis |
ICCAD
1995
IEEE
13 years 12 months ago
1995
IEEE
Abstract—We propose the use of the logic S1S as a mathematical framework for studying the synthesis of sequential designs. We will show that this leads to simple and mathematical...
FPGA
2007
ACM
14 years 2 months ago
2007
ACM
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
CAV
2006
Springer
14 years 4 days ago
2006
Springer
The relationship between two well established formalisms for temporal reasoning is first investigated, namely between Allen's interval algebra (or Allen's temporal logic,...
ISPD
2003
ACM
14 years 1 months ago
2003
ACM
In this paper we present the Gain-based Logic Block Array (GLA), a new via-programmable regular fabric. GLA is an array of Gainbased Logic Blocks (GLBs). The GLB is a semi-univers...