564 search results - page 23 / 113 » Wireplanning in logic synthesis |
FPGA
2009
ACM
14 years 3 months ago
2009
ACM
In recent years, the maximum logic capacity of each successive FPGA family has been increasing by more than 50%, which motivates scalable solutions. Meanwhile, academic research i...
ENTCS
2006
13 years 8 months ago
2006
A compiler that automatically translates recursive function definitions in higher order logic to clocked synchronous hardware is described. Compilation is by mechanised proof in t...
ACSD
2004
IEEE
14 years 5 days ago
2004
IEEE
The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of...
DAC
1994
ACM
14 years 16 days ago
1994
ACM
Manufacturing disturbances are inevitable in the fabrication of integrated circuits. These disturbances will result in variations in the delay speci cations of manufactured circui...
FOSSACS
2008
Springer
13 years 10 months ago
2008
Springer
Abstract. We present a novel coalgebraic logic for deterministic Mealy machines that is sound, complete and expressive w.r.t. bisimulation. Every finite Mealy machine corresponds t...