Sciweavers

564 search results - page 25 / 113
» Wireplanning in logic synthesis
Sort
View
GLVLSI
2003
IEEE
134views VLSI» more  GLVLSI 2003»
14 years 1 months ago
Modeling QCA for area minimization in logic synthesis
Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device impro...
Nadine Gergel, Shana Craft, John Lach
DATE
2010
IEEE
175views Hardware» more  DATE 2010»
14 years 13 days ago
Approximate logic synthesis for error tolerant applications
─ Error tolerance formally captures the notion that – for a wide variety of applications including audio, video, graphics, and wireless communications – a defective chip that...
Doochul Shin, Sandeep K. Gupta
DAC
2005
ACM
14 years 9 months ago
A new canonical form for fast boolean matching in logic synthesis and verification
? An efficient and compact canonical form is proposed for the Boolean matching problem under permutation and complementation of variables. In addition an efficient algorithm for co...
Afshin Abdollahi, Massoud Pedram
IPPS
1997
IEEE
14 years 19 days ago
A Comparison of Parallel Approaches for Algebraic Factorization in Logic Synthesis
Algebraic factorization is an extremely important part of any logic synthesis system but is computationally expensive. Hence it is important to look at parallel processing to spee...
Sumit Roy, Prithviraj Banerjee
GECCO
2005
Springer
128views Optimization» more  GECCO 2005»
14 years 1 months ago
Fractional dynamic fitness functions for GA-based circuit design
This paper proposes and analyses the performance of a Genetic Algorithm (GA) using two new concepts, namely a static fitness function including a discontinuity measure and a fract...
Cecília Reis, José António Te...