Sciweavers

564 search results - page 28 / 113
» Wireplanning in logic synthesis
Sort
View
DATE
2008
IEEE
124views Hardware» more  DATE 2008»
14 years 2 months ago
Logic Synthesis with Nanowire Crossbar: Reality Check and Standard Cell-based Integration
Nanowire crossbar is one of the most promising circuit solutions for nanoelectronics. We show nanowire crossbars do not scale well in terms of logic density and speed. We conseque...
Mian Dong, Lin Zhong
LOPSTR
1998
Springer
14 years 20 days ago
Inductive Synthesis of Logic Programs by Composition of Combinatory Program Schemes
Based on a variable-free combinatory form of definite clause logic programs we outline a methodology and supporting program environment CombInduce for inducing well-moded logic pro...
Andreas Hamfelt, Jørgen Fischer Nilsson
DATE
1997
IEEE
75views Hardware» more  DATE 1997»
14 years 20 days ago
Using constraint logic programming in memory synthesis for general purpose computers
In modern computer systems the performance is dominated by the memory performance. Currently, there is neither a systematic design methodology nor a tool for the design of memory ...
Renate Beckmann, Jürgen Herrmann
TCAD
2008
112views more  TCAD 2008»
13 years 8 months ago
Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs
Boolean matching is one of the enabling techniques for technology mapping and logic resynthesis of Field Programmable Gate Array (FPGA). SAT-based Boolean matching (SAT-BM) has bee...
Yu Hu, Victor Shih, Rupak Majumdar, Lei He
ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
14 years 5 months ago
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
Yu Hu, Satyaki Das, Steven Trimberger, Lei He