564 search results - page 45 / 113 » Wireplanning in logic synthesis |
ICCAD
2007
IEEE
14 years 2 months ago
2007
IEEE
—In latency-insensitive design shell modules are used to encapsulate system components (pearls) in order to interface them with the given latency-insensitive protocol and dynamic...
FMCAD
2006
Springer
14 years 4 days ago
2006
Springer
We present an approach to automatic synthesis of specifications given in Linear Time Logic. The approach is based on a translation through universal co-B
EON
2008
13 years 10 months ago
2008
We reuse here the framework, the setting, and the semantic modelling for the automated synthesis of the SWS Challenge Mediator presented in the companion paper [5], and show how to...
FSTTCS
2009
Springer
14 years 11 days ago
2009
Springer
ABSTRACT. Church's Problem asks for the construction of a procedure which, given a logical specification on sequence pairs, realizes for any input sequence I an output sequen...
DAC
2009
ACM
14 years 9 months ago
2009
ACM
This paper describes a function-based timing-driven optimization technique for the synthesis of multi-level logic circuits. Motivated by the principles of parallel prefix computat...