Timing-driven optimization using lookahead logic circuits

This paper describes a function-based timing-driven optimization technique for the synthesis of multi-level logic circuits. Motivated by the principles of parallel prefix computation, the proposed timingdriven optimization produces circuits with "lookahead" properties due to the inherent parallelism among the synthesized sub-circuits. Lookahead logic circuits are synthesized by using global critical path sensitization information to reduce the Boolean functions of the nodes in the technology-independent representation of the logic circuit. Unlike prior function-based timing-driven optimization techniques, where synthesis of the decomposition functions is potentially expensive, the proposed technique has the advantage that the decomposition function is embedded in the synthesized circuit. On average, the proposed technique reduces the number of logic levels (the mapped delay) of the final circuit by 40%, 56%, and 22% (21%, 56% and 10%) over the best results of SIS, ABC, and S...

• Type: Conference
• Year: 2009
• Where: DAC
• Authors: Mihir R. Choudhury, Kartik Mohanram
• Keywords: Computer Architecture, DAC 2009, Function-based Timing-driven Optimization, Multi-level Logic Circuits, Optimization Produces Circuits