564 search results - page 52 / 113 » Wireplanning in logic synthesis |
CONCUR
2006
Springer
14 years 7 days ago
2006
Springer
Abstract. We consider the control problem for timed automata against specifications given as MTL formulas. The logic MTL is a linear-time timed temporal logic which extends LTL wit...
ICCAD
2002
IEEE
14 years 5 months ago
2002
IEEE
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
ICCS
2009
Springer
14 years 3 months ago
2009
Springer
This paper is an extended abstract of the talk given at ICCS’09. Rules have long been considered as an essential component of knowledge-based systems. We focus here on conceptual...
JNSM
2008
13 years 8 months ago
2008
There is a large conceptual gap between end-to-end infrastructure requirements and detailed component configuration implementing those requirements. Today, this gap is manually br...
FPL
2005
Springer
14 years 2 months ago
2005
Springer
This paper describes a novel Field Programmable Gate Array (FPGA) logic synthesis technique which determines if a logic function can be implemented in a given programmable circuit...