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» Wireplanning in logic synthesis
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DLOG
2006
13 years 8 months ago
Tableau Caching for Description Logics with Inverse and Transitive Roles
Abstract. Modern description logic (DL) reasoners are known to be less efficient for DLs with inverse roles. The current loss of performance is largely due to the missing applicabi...
Yu Ding, Volker Haarslev
FPGA
2005
ACM
95views FPGA» more  FPGA 2005»
14 years 28 days ago
The Stratix II logic and routing architecture
This paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be p...
David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaugh...
EDCC
2006
Springer
13 years 11 months ago
SEU Mitigation Techniques for Microprocessor Control Logic
The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance de...
T. S. Ganesh, Viswanathan Subramanian, Arun K. Som...
SIGLEX
1991
13 years 11 months ago
Logical Structures in the Lexicon
The lexical entry for a word must contain all the information needed to construct a semantic representation for sentences that contain the word. Because of that requirement, the f...
John F. Sowa
RSCTC
2004
Springer
134views Fuzzy Logic» more  RSCTC 2004»
14 years 23 days ago
Rough Set Methods in Approximation of Hierarchical Concepts
Abstract. Many learning methods ignore domain knowledge in synthesis of concept approximation. We propose to use hierarchical schemes for learning approximations of complex concept...
Jan G. Bazan, Sinh Hoa Nguyen, Hung Son Nguyen, An...